In a coherent light communication system, after completing optical-to-electrical conversion, a receiver needs to convert an analog electrical signal into a digital signal by using an analog to digital converter (ADC) for subsequent digital-domain algorithm processing. A clock recovery circuit is a critical module ensuring that a rate at which the ADC converts the analog signal into the digital signal is corresponding to a rate at which a transmitter sends a signal. In the clock recovery circuit, a phase detector determines a deviation of a current sampling rate from a target sampling rate, and a feedback control circuit adjusts an actual sampling rate of the ADC, to achieve an objective that the receiver is synchronous with the transmitter.
In the prior art, in the clock recovery circuit, the phase detector performs, based on a waveform, calculation on a signal received by a receiving end, to obtain a phase detection signal. The phase detection signal may be fed back, after digital filtering, to a voltage-controlled oscillator device that simulates a peripheral circuit, so that the voltage-controlled oscillator device adjusts the actual sampling rate of the ADC of the receiver. Alternatively, the phase detection signal may be fed back to a numerically controlled oscillator, so that the numerically controlled oscillator completes numeral interpolation on sampling sequences of the ADC of the receiver.
However, in coherent light communication, a waveform of a signal is affected by factors such as random polarization rotation, a polarization-dependent loss, polarization mode dispersion, chromatic dispersion, a channel bandwidth impairment, and a frequency offset between transmit and receive lasers in an optical fiber. Consequently, an error of the phase detection signal obtained by a conventional phase detector through calculation based on the waveform is relatively large.